GPT-Synopsys brings together OpenAI frontier models with Synopsys' EDA technology and domain expertise, enabling the specialized model [to] directly operate Synopsys' tools. Engineers will delegate design objectives … with agents running tools, interpreting results, implementing changes, and iterating toward verified outcomes for engineer review.
“Agents will do all the engineering work. Engineers will delegate and review.” Lol, no, what the engineers are gonna do is get laid off.
Chips design is expensive. Partly because of engineering costs, partly because of manufacturing costs.
If costs go down enough,because of LLM's and possible manufacturing innovations, more chips will be designed, so maybe this will partially offset job loses.
A question to those active in chip design industry: Are formal methods and formally proving a design more prevalent and normal in this industry compared to general software development?
Like for a Arm microcontroller design, do engineers thoroughly test and formally prove the correct functionality of every component? If that's the case, why silicon errata is a thing?
> I see you are using Cadence IP in your project, unfortunately this is not allowed per the terms and conditions and you will be reported to the authorities
Also : create proprietary locked down eda->no data to train models->models suck at it->reach out to ai lab to rl on it -> expect users to pay for eda and the model.
... > I see you are using Cadence IP in your project, unfortunately this is not allowed per the terms and conditions and you will be reported to the authorities
EXACTLY, prepare to self deport immediately, push <proceed> to execute
We just buried an ASIC design that was nearly finished.
Reason: There was a deviation that would've needed a mask change, but because of AI chip demand, the manufacturer wanted so much money for it, that we said screw it.
So we now have AI powered chip design tools that make chip design cheaper, but because of AI, chip manufacturing has become so expensive, that we can't afford it anymore.
Having written a lot of Tcl glue for PrimeTime and ICC, the hard part was never writing the constraints, it was knowing which timing violation to actually believe.
Toolcalls will end up disappearing to the other side and then you can download the end result - at a price - or arrange for manufacturing, but you'll have no idea about what is in the nice & shiny black box.
If costs go down enough,because of LLM's and possible manufacturing innovations, more chips will be designed, so maybe this will partially offset job loses.
Like for a Arm microcontroller design, do engineers thoroughly test and formally prove the correct functionality of every component? If that's the case, why silicon errata is a thing?
Also : create proprietary locked down eda->no data to train models->models suck at it->reach out to ai lab to rl on it -> expect users to pay for eda and the model.
EXACTLY, prepare to self deport immediately, push <proceed> to execute
So we now have AI powered chip design tools that make chip design cheaper, but because of AI, chip manufacturing has become so expensive, that we can't afford it anymore.
Nice.
Manufacturers choosing not to scale with demand or not being able to scale with demand
Is what constrained the supply.
Hopefully will be fixed within a decade , then it’s cool new stuff all the way.
I am not sure if Nvidia want to send their chip designs to OpenAI.
Toolcalls will end up disappearing to the other side and then you can download the end result - at a price - or arrange for manufacturing, but you'll have no idea about what is in the nice & shiny black box.
Can't wait for vibe coded SoCs.